![]() ![]() People talk about the audio being inserted in an 'analog' fashion into HDMI but I think that's a misunderstanding that comes from the signal being sent over differential/'balanced' which has +,-, and neutral so it looks like a normal full waveform rather than a V+/V0 'digital' signal. slow rise/slow fall) since it gets so many more positions to poll the data before decoding and re-creation of the payload. HDMI operates on such a high frequency signals (165Mhz minimum in the 1.0 standard with a 10x synthesized clock to pick it even further apart) and has error correction that I suspect it has no issue cleaning up weak or malformed signals (i.e. ![]() The issue however, as seen in Michael's experiment in a similar vein is a less than ideal signal strength and/or s/n ratio. Information layer: HDMI encoded -> BlackBox -> I2S synch -> USBStreamer Async PCM conversion Physical layer: HDMI cable -> BlackBox -> shielded HDMI/LVDS cabling -> Female HDMI/LVDS breakout board -> manual pinout to I2S on USBStreamer via pre-terminated ribbon wireĮlectrical layer: LVDS/Differential up to 3v -> BlackBox -> to 3.3v -> 3.3v unbalanced -> digital signal amplifier/isolation -> 5v unbalanced -> Stepdown I should be more strict in my language usage since I realize I'm now adding confusion: Yes, the plan is to just use the I2S-over-HDMI port out on this extraction board for multi-channel audio, then use a female HDMI port breakout board to wire as appropriate to a I2S-USB conversion board (using pre-cut/terminated 3" ribbons, not quite as good as printed circuits but should be sufficient). There are other isolators like this digital isolator which has a smaller rise and fall time but the total transit across the chip is larger and the pulse distortion doesn't seem like it would be much better? The range of delay however is somewhat variable but still should fall within the tolerances if we're only using a 6Mhz signal I think. Assuming 1 bit per hz as the worst efficiency/naively encoded it should have enough overall bandwidth (33Mhz) and the saturation delay shouldn't be an issue so long as every signal has the same delay and the frames are being asynch reclocked on the other end. Worst case scenario using the first chip is: So I believe I need to use a chip that supports up to 6.144 Mhz. The lower boundary will be set by the MClk since it will be the highest frequency signal and all other clocks will be a divisible subset of it. If you're sampling an 8 signal there will be 8 I2S channels: 4 data channels, 2 'polarity/frame' channels/a 'left' and a 'right' clock, and 2 timing (a frame/word clock and Master clock). This one matters mostly if you're using I2S in a bidirectional fashion Saturation delays introduced specifically by electro-optical isolation which can be fixed by maintaining a partial load on the diodes and/or using a different form of isolation like capacitive coupling. Propagation time across the isolator (which if every line is subject to the same delay isn't an issue except for live latency)ģ. Rise and Fall minimum times to ensure each clock beat is sampled and reproduced (required minimum times dictated by the MClk)Ģ. This paper implies there are three main issues with electro-optical isolation:ġ. Then you would take the output and feed it to the next system.īut then I started looking into the tolerances required to be transparent to the I2S slaved receiving chip and became less sure. Originally I thought it would be as simple as taking the I2S pinout and running each leg through an electro-optical isolator like this 4/0 since the data flow is unidirectional in this case. I am somewhat confused about the tolerances required for I2S galvanic isolation.
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